The present invention relates to a semi-conductor integrated circuit device and a fabrication technique thereof or more, particularly to a technique effectively applicable to a semiconductor integrated circuit device comprising a DRAM (dynamic random access memory) having a memory cell of stacked capacitor structure with an information storage capacitor arranged on a memory cell-selecting MISFET and also to a technique for connecting a semiconductor region and an electrical wiring metal to each other through a titanium (Ti) silicide layer.
In order to compensate for the reduction in the accumulated charge (Cs) of the information storage capacitor with the miniaturization of the memory cell, a large-capacity DRAM recently developed has a stacked capacitor structure with an information storage capacitor above a memory cell-selecting MISFET.
The information storage capacitor of stacked capacitor structure is formed by depositing a storage electrode (lower electrode), a capacitive insulating film and a plate electrode (upper electrode) in that order. The storage electrode of the information storage capacitor is composed of polycrystal silicon doped with n-type impurities (phosphorus) and is connected to one of the semiconductor regions (source and drain regions) of a memory cell-selecting n-channel MISFET. The plate electrode is composed as an electrode shared by a plurality of memory cells and is supplied with a predetermined fixed potential.
A bit line for writing and reading data is arranged above the memory cells. The bit line is connected to the other one of the semiconductor regions (source and drain regions) of the memory cell-selecting MISFET through a contact hole opened to an insulating film covering the memory cells. The bit line is composed of a low-resistance metal material in order to assure high-speed data write and read operation.
The height (from the substrate surface) of the memory array of the DRAM having memory cells of stacked capacitor structure described above is greater than that of the peripheral circuit be an amount substantially equal to the height of the information storage capacitor. As a result, with the miniaturization of the memory cell, the aspect ratio between the semiconductor regions of the memory cell-selecting MISFET and the contact holes for connecting the bit line is considerably increased, thereby making it difficult to deposit a metal material for the bit line sufficiently in the contact holes.
One known solution attempt of overcoming this problem is with regard to the DRAM described in JP-A-7-142604, which corresponds to U.S. patent application Ser. No. 08/341,966 filed on Nov. 16, 1994, and which is fabricated by employing a polycrystalline silicon plug technique in which a polycrystal silicon film of the same conductivity type (n-type) as that of the semiconductor regions of the memory cell-selecting MISFET is filled in the contact holes. In this technique, contact holes reaching the semiconductor regions of a memory-cell selecting MISFET are formed through an insulating film covering memory cells, a sufficient amount of polycrystal silicon film is filled in each contact hole using the CVD process having a superior step coverage, and then an unrequired polycrystal silicon film remaining on the insulating film is removed by etching (etch back).
The use of a (n-type) polycrystal silicon film as a plug material filled in the contact hole is effective not only as a measure to secure the conduction of the bit line but also to reduce the memory cell size. Specifically, the DRAM with a reduced memory cell size has such a miniscule diameter of the contact hole for the bit line that in the case where a mask misalignment occurs between the contact hole and the semiconductor regions of the memory cell-selecting MISFET when opening the contact hole by etching with photoresist as a mask, the contact area between the semiconductor regions and the plug material filled subsequently in the contact hole is reduced resulting in an increased contact resistance. In the case where a polycrystal silicon film of the same conductivity type (n-type) as the semiconductor regions is used as a plug material, by contrast, the (n-type) impurities in the polycrystal silicon film are diffused into the substrate and the contact resistance is reduced. The mask alignment margin can thus be reduced between the semiconductor regions and the contact holes.
Also, in the DRAM disclosed in the above-mentioned patent publication, the bit line is composed of a tungsten (W) film, and the first layer of wiring connected to the semiconductor regions (source and drain regions) of a complementary MISFET (CMOSFET) constituting the peripheral circuits is composed of a W film in the same layer as the bit line.
Using tungsten (W) for the wiring of the first layer of the peripheral circuit and for the bit line provides a high electromigration endurance as compared with wirings formed aluminum, (Al) thereby resulting in a improvement in the wiring life of a miniaturized DRAM. The above-mentioned technique of filling a polycrystalline silicon plug in the bit-line contact holes is indispensable for constructing the bit line and the first layer of the peripheral circuit by the W film in the same layer. This is by reason of the fact that in the case where the plug material is not filled in the bit-line contact hole, it is necessary to fill the plug material in the (bit-line) contact hole of a very large aspect ratio and the contact hole (for the peripheral circuit) small in aspect ratio at the same time, thereby increasing the process burden. The above-mentioned scheme, however, fails to describe anything about the formation of a Ti silicide layer.
The present inventors have thoroughly examined the problems which occur when forming the first layer of the wiring of the peripheral circuit and the bit line in the same layer of a W film in a DRAM having memory cells of stacked capacitor structure. The findings of this effect are described briefly below.
Generally, a W film is known to have a low adherence to an insulating film such as a silicon oxide film. Also, at a contact point between the wiring and the substrate, the metal material constituting the wiring and the silicon constituting the substrate react with each other to form a silicide layer. The silicide (tungsten silicide) layer produced by the reaction between the W film and the silicon substrate exerts a great stress on the substrate. As a result, in the case where the first layer of the wiring of the peripheral circuit is composed of a W film, therefore, it is necessary to form under the W film such a metal film that forms a silicide layer to provide a high quality adherence to the insulating film and exert a small stress when reacting with the silicon substrate.
Titanium (Ti) has a superior adherence to an insulating film, and the Ti silicide (TiSix, x.ltoreq.2) formed by reaction with the silicon substrate exerts only a small stress on the substrate. Therefore, titanium provides a suitable material as a metal film formed under the W film. Also, to form a Ti silicide layer in the interface between the first layer of wiring and the semiconductor regions (source and drain regions) of the MISFET constituting the peripheral circuit is an effective measure for reducing the contact resistance of the wiring.
The Ti film, however, poses the problem that it reacts with WF.sub.6 making up a source gas produced when depositing the W film by the DVD process and forms an undesirable reaction layer on the film surface. In the case where a W film is deposited on the Ti film, therefore, a barrier layer which is resistant to reaction with WF.sub.6 and having a high adherence with both the Ti film and the W film is required to be formed between the Ti film and the W film. A preferable barrier layer is a TiN (titanium nitride) film.
A method of forming the first layer of wiring of the peripheral circuit and the bit line at the same time with a W-TiN-Ti film lamination is as follows. First, a polycrystalline silicon plug is filled in the bit-line contact holes formed in an insulating film covering memory cells, and then contact holes are formed in the insulating film covering a MISFET of the peripheral circuit. As the next step, a Ti film and a TiN film are deposited continuously by sputtering on the insulating film. The substrate is annealed in the nitrogen environment, so that the reaction is caused between the Ti film and the silicon (substrate) thereby to form a Ti silicide layer in the interface between the Ti film and the silicon substrate. After that, a W film is deposited by CVD on the TiN film. The W film and the underlying TiN and Ti films are patterned by etching with a photoresist as a mask thereby to form the first layer of wiring of the peripheral circuit and the bit line.
The present inventors, after examining the above-mentioned process further, have found the following problems.
As described above, in the process of forming the first layer of wiring of the peripheral circuit and the bit line by a W-TiN-Ti film lamination, the polycrystalline silicon plug is filled in the bit-line contact holes in advance of the deposition of a TiN-Ti film. In forming a Ti silicide layer in the interface between the Ti film and the silicon substrate by annealing the substrate, therefore, a Ti silicide layer is formed in the interface between the polycrystalline silicon plug and the Ti film in the bit-line contact holes.
Once the Ti silicide layer is formed on the polycrystalline silicon plug, however, the interface between the polycrystalline silicon plug and the Ti silicide layer may be separated, often causing a conduction failure of the bit line. An examination of the cause has led to the findings that there is a correlation between the separation frequency and the thickness of the Ti silicide layer formed on the polycrystalline silicon plug.
FIG. 25 is a graph showing the result of study made on the relation between the thickness of the Ti silicide layer and the interface separation. As shown in FIG. 25, separation occurs for the thickness of the Ti silicide layer higher than a certain value. The smaller the diameter of the contact hole, the smaller the thickness with which the separation occurs. A possible cause of this separation is that with the increase in the thickness of the Ti silicide layer, the interface between the polycrystalline silicon plug and the Ti silicide layer is subjected to the stress due to the volume reduction caused by the formation of the Ti silicide layer and the stress due to the crystallization of the TiN film.
In the case where the Ti silicide layer is formed in the interface between the Ti film and the silicon substrate, on the other hand, the contact resistance would undesirably increase unless a certain degree of thickness is secured of the Ti silicide layer. Especially in the case where a Ti silicide layer is formed on the surface of the source and drain regions (p-type semiconductor regions) of a p-channel MISFET, as shown in FIG. 26, a decreased thickness of the Ti silicide layer is found to increase the contact resistance considerably.
A conventional technique for reducing the resistance of the contact section for electrically connecting the surface of a silicon substrate and a metal wiring is disclosed, for example, in JP-A-07-78821 (hereinafter referred to the well-known example), in which a titanium silicide film is formed between the silicon substrate and the metal wiring.
With the increase in the thickness of the titanium silicide film and also with the decrease in the diameter of the contact hole, however, the titanium silicide film is more easily separated, which is a stumbling block to higher integration and miniaturization of a semiconductor device.
For a low contact resistance to be obtained by forming a silicide film in the interface between silicon and a metal, the titanium silicide film formed (especially, TiSi.sub.2 di-silicide) is required to have a certain degree of thickness. Since titanium silicide is formed by heat treatment of the silicon deposited with a titanium film thereon, however, the volume change of the film generates a stress in the film.
This internal stress of the film increases the stress generated in the neighborhood of the interface between the titanium silicide film and the silicon. Experiments and analyses have made it clear that the average stress generated in the interface increases with the decrease in the size of the contact hole and also with the increase in the thickness of the titanium silicide layer, thereby causing the separation of the titanium silicide film.
As described above, in the case where a polycrystalline silicon plug is filled in the bit-line contact hole to form the first layer of wiring of the peripheral circuit and a bit line at the same time with a W-TiN-Ti film lamination, it is difficult to secure the conduction reliability of the bit line and to reduce the contact resistance of the wiring connected to the source and drain regions of the MISFET of the peripheral circuit at the same time.